One type of known non-volatile storage devices is erasable programmable read only memories ("EPROMs"). The EPROMs can be programmed (written) by a user.
In order to erase the EPROMs, it is necessary to irradiate the memory cells of the EPROMs with ultraviolet rays. The entire memory cell array is collectively erased by the ultraviolet ray irradiation. For this purpose, the EPROM must be removed from a substrate each time it is rewritten with new data.
Because the EPROMs have a small memory cell area, they are suitable for large capacity storage. The EPROMs, however, require a window-provided package because the data thereof is erased by ultraviolet ray irradiation. Furthermore, because reprogramming is carried out using a writing device called programmer (or writer), the EPROM needs to be removed from the system when writing data.
Conventionally known electrically erasable programmable read only memories ("EEPROMs") can be electrically reprogrammed within systems in which they are provided. The area of a memory cell of the EEPROMs is, however, about 1.5 to 2 times as large as that of the memory cell of the EPROMs. This results in that the EEPROMs are larger and more costly than the EPROMs. Therefore, it is difficult to provide the EEPROMs with large capacities.
Thus, recently, a memory called "flash memory" (or flash EPROM) has been developed as an intermediate memory between the EPROM and the EEPROM.
The flash memory is a non-volatile semiconductor memory having a function of electrically erasing data of a chip at a time or electrically erasing data of memory cells positioned in a certain region called a sector or a block at a time. The memory cell of the flash memory has an area almost equal to that of the memory cell of the EPROM.
A memory cell, shown in FIG. 5, for the flash memory is known from U.S. Pat. No. 5,249,158 and U.S. Pat. No. 5,245,570. The memory cell 501 shown in FIG. 5 has a floating gate type field effect transistor structure in which one bit (one cell) is composed of one element. Thus, the memory cell 501 can be highly integrated with ease.
Writing data to the memory cell 501 is performed by applying about 12 volts to a control gate electrode 502, about 7 volts to a drain 503, and 0 volts to a source 505 to thereby inject hot electrons generated in the vicinity of a drain junction to a floating gate electrode 506. By the data write, the threshold voltage of the memory cell 501 with respect to the control gate electrode 502 becomes high.
By arranging the memory cell 501 shown in FIG. 5 to have a multi-value, higher integration will be easily achieved. For example, the memory cell 501 may have a plurality of threshold voltages Vth at which the memory cell takes a 2.sup.n state at intervals of several hundred millivolts.
In this case, the writing of data to the memory cell 501 is performed by applying 0 volts to the source 505, pulses of several microseconds to the floating gate electrode 506 at about 12 volts, and pulses of several microseconds to the drain 503 at about 7 volts to thereby inject hot electrons generated in the vicinity of the drain junction to the floating gate electrode 506.
By the data writing, the threshold voltage Vth of the memory cell 501 with respect to the control gate electrode 502 increases. The threshold voltage Vth can be varied by changing the voltage to be applied to the control gate electrode 502, the drain voltage or the pulse to be applied to the control gate electrode 502 or the drain 503.
In order to erase data from the memory cell 501, the floating gate electrode 506 is grounded and a positive high voltage (about 12 volts) is applied to the source 505. Thus, high electric field is generated between the floating gate electrode 506 and the source 505, and electrons stored in the floating gate electrode 506 are drawn to the source 505 by utilizing the tunnel phenomenon through a thin gate oxide film.
Normally, data is erased block by block (for example, in 16K bytes or 64K bytes). The data erasure causes the threshold voltage Vth of the memory cell 501 with respect to the control gate electrode 502 to drop. The memory cell 501 does not have a selection transistor. Thus, when the threshold voltage Vth becomes negative due to excess erasure, a fatal disadvantage that data cannot be correctly read takes place.
When the memory cell 501 stores binary data, the memory cell is read by applying 0 volts to the source 505, a low voltage about 1 volt to the drain 503, and about 5 volts to the control gate electrode 502. The size of a channel current flowing at this time corresponds to information "1" or "0". Specifically, a larger channel current corresponds to information "1" and a smaller channel current corresponds to information "0". This fact is utilized for the data reading. The reason a low voltage is applied to the drain 503 is to prevent parasitic write operation (so-called "soft write") from being performed.
When the memory cell 501 stores multi-valued data, in reading the memory cell 501, 0 volts is applied to the source 505, a low voltage of about one volt is applied to the drain 503, and a voltage to be applied to the control gate electrode 502 is changed. The multi-valued memory data is read by utilizing the value of a voltage applied to the control gate electrode 502 at which voltage the channel electric current flows.
In the memory cell 501, because writing is executed at the drain side and erasure is executed at the source side, it is preferable to optimize junction profiles individually for each operation. That is, the source 505 and the drain 503 are asymmetric in structure relative to each other; in the drain junction, an electric field convergence type profile is used to enhance writing efficiency; and in the source junction, an electric field relaxation type profile allowing application of a high voltage to the source 505 is adopted.
In the method of applying a high voltage to the source 505 in the erase operation, it is necessary to increase the withstanding voltage in the source junction. Thus, it is difficult to make the structure at the source electrode side fine. Further, hot holes are generated in the neighborhood of the source 505 and a part of the hot holes is trapped inside the tunnel insulation film. Thus, reliability of the cell deteriorates.
As another example of data erasure, negative gate erasing method is known. In this method, a negative voltage (about -10 volts) is applied to the control gate electrode 502, and a power voltage (about 5 volts) is applied to the source 505, and data is erased by tunnel electric current. One of the advantages of the negative erasure method is that because a low voltage is applied to the source 505 at a data erasure time, the junction withstanding voltage at the source side is allowed to be low and that it is possible to reduce the length of the gate of the memory cell. Further, the negative erasure method allows the size of a erase block to be small so that data can be erased easily sector by sector.
In the data erasing method of applying a high electric field to the source 505, tunnel electric current flows between bands and the value of the total electric current of an entire chip is as high as several milliamperes. Thus, it is difficult to use a boosting circuit in the data erasure method. Accordingly, heretofore, an erasing high voltage Vpp is supplied from the outside of the chip.
In the negative gate erasing method, it is possible to supply a power voltage Vcc (5 or 3 volts) to the source 505. Thus, the negative gate erasure method has an advantage that operation of the memory by a single power source can be realized comparatively easily.
In the method of using hot electrons for writing, electric current about 1 mA flows per memory cell in the data-writing time. Thus, a known particular type of flash memory uses FN (Fowler-Nordheim) tunnel electric current to reduce electric current flowing per memory cell in the data-writing time, like the EPROMs.
Meanwhile, as semiconductor-manufacturing process has become fine and battery-driven portable equipment has been widely used, a low voltage is demanded for an operating power source. Thus, there is a demand for development of a memory that is operated by a single power supply of 3.3 volts, not 5 volts. Thus, research and development are energetically made in compliance with such a demand.
In reading data with the power source of 3.3 volts, in the existing flash EPROMs, a supply electric potential (Vcc=3.3 volts) is applied to a control gate line (i.e., a word line). Otherwise, to accomplish a high-speed operation and expand an operation margin, an internally increased voltage of about 5 volts are applied to the control gate line.
Such a non-volatile semiconductor memories have more operation states than random access memories (RAMs) capable of writing and reading data in a short time. The operation states include a write state, a block erasure state, a simultaneous entire chip erasure state, and a status-register reading state. When associating such large a number of operation states of the non-volatile semiconductor memory with combinations of external control signals (CE, WE, etc.), the control signals that are used for the EPROMs and the EEPROMs are insufficient. Thus, it is necessary to add new control signals, which makes the memories difficult to operate.
In order to overcome such a problem, as disclosed in the U.S. Pat. No. 5,053,990, a command method which does not use an increased number of control signal lines has been proposed and come to be widely used. In the non-volatile semiconductor memories adopting the command method, a command entered by a user is sent to a command state machine (CSM). The command is recognized by the command state machine. Based on the recognition made by the command state machine, a write state machine (WSM) executes an operation (erase, write, etc.) corresponding to the command.
A non-volatile semiconductor memory of this kind is also disclosed in U.S. Pat. No. 5,249,158 in which the chip is divided non-uniformly into erase blocks. U.S. Pat. No. 5,245,570 also discloses a non-volatile semiconductor memory of such a kind in which the erase blocks are of the same size.
In addition, a non-volatile semiconductor memory in which write and erase operations are performed by means of FN tunnel electric current is also known. A memory cell system called NAND type in which 8 or 16 memory cells are connected in series is also known. The NAND type memory cell system is slower than the NOR type memory cell system in reading speed, but has an advantage in that the size thereof can be reduced.
As described previously, normally one memory cell stores a binary data (one bit). Research and development are made to allow one memory cell to store multi-valued data such as a quaquaternary value (two bits), an octal value (three bits), and a hexadecimal value (four bits).
FIG. 11 shows a non-volatile semiconductor memory (flash EEPROM) 110, as disclosed in the U.S. Pat. No. 5,365,486, capable of performing refresh operation. As shown in FIG. 11, addresses and data are supplied to the non-volatile memory 110 from the outside. The non-volatile memory 110 has a column decoder 112, a word line decoder 114, and read/write/erasure circuitry 116. The read/write/erasure circuitry 116 is connected with both the column decoder 112 and the word line decoder 114. A memory cell array in the non-volatile memory 110 is divided into various sectors 118, 120, 122, 124, 126, and 128. The sectors 118, 120, and 122 share common bit lines extending from the column decoder 112. The sectors 124, 126, and 128 also share common bit lines extending from the column decoder 112. Further, the sectors 118 and 124 share common word lines from the word line decoder 114. Similarly, the sectors 120 and 126, and the sectors 122 and 128 share common word lines extending from the word line decoder 114, respectively. All of the bit lines from the column decoder 112 are coupled to a sense amplifier 130, which is used to sense data on various bits and transmit the data for external communications. Refresh circuitry 132 is coupled to the column decoder 112, the word line decoder 114, and the read/write/erasure circuitry 116. Memory cells constituting one sector shown in FIG. 11 are arranged as shown in FIG. 12 which shows a typical array of the memory cells. The memory cells, indicated by reference symbol MC, are coupled to the column decoder 112 and the word line decoder 114. The refresh circuitry 132 is coupled to the output of a sense amplifier 154. An erase cycle counter 156 is coupled to the refresh circuitry 132 and receives inputs from other sectors. The frequency with which the refresh circuitry 132 reads each array of memory cells MC is determined by the erase cycle counter 156. The erase cycle counter 156 counts the number of erase cycles performed in sectors electrically associated with the sector shown in FIG. 12. That is, the erase cycle counter 156 counts the number of erase cycles which could cause disturb conditions in the sector shown in FIG. 12. The erase cycle counter 156 is set according to the particular needs of the system in which the non-volatile semiconductor memory 110 is included. For example, the erase cycle counter 156 is set at 10, so that refresh occurs after any 10 erase cycles from any of the sectors that could cause disturb conditions within the sector shown in FIG. 12. In another example, the erase cycle counter 156 is set at one.
Referring to FIG. 11, for example, once a total of 10 erase cycles has been performed in the sectors 120, 122, and 124, a refresh for the sector 118 is performed, with the erase cycle counter 156 set at 10. For example, if two erase cycles were performed in the sector 120, five in the sector 122, and three in the sector 124, a refresh cycle would be performed in the sector 118.
The refresh circuitry 132 controls the column decoder 112 and the word line decoder 114 for refresh of each sector in the non-volatile semiconductor memory 110. Further, the erase cycle counter 156 counts erase cycles in each sector such that the refresh circuit 132 refreshes the appropriate sectors as needed. The refresh operation is performed in accordance with the flowchart of FIG. 13.
The refresh operation is described below by using the flowchart of FIG. 13. Initially, the program goes to step S42 at which a particular cell is read at an elevated control gate voltage, Vcg (for example, 7 volts), to determine whether the memory cell has been programmed. Since programmed memory cells should not conduct, placing an elevated voltage on the control gate of a particular cell will result in conduction unless that cell is programmed, and its floating gate has enough charge on it to prevent conduction. If a programmed memory cell has been disturbed and some its charge is gone, for example, through word line stress or bit line stress, electric current flows as a result of application of the elevated voltage to the control gate. Thus, at decision step S44, an initial determination is made whether the memory cell is programmed. If no conduction occurs through the cell at the elevated control gate voltage applied at step S42, then the cell has been programmed and has not been disturbed. Thus, data of the next memory cell is read at the following step S46. If, however, it is determined at step S44 that conduction has occurred after application of the elevated control gate voltage at step S42, the program goes to step S48. At step S48, the particular bit is read at a lowered control gate voltage (for example, 5 volts). The lowered control gate voltage should be high enough to ensure conduction if the bit is an erased bit, and not so low as to result in no conduction for an erased bit that has been disturbed through a soft write. It is determined at decision step S50 whether or not the cell is a programmed cell. If there is conduction at the lowered control gate voltage, then the cell is an erased cell and no refresh is necessary, and the next cell is read at step S46. However, if no conduction occurs after application of the lowered control gate voltage to the particular cell, it is determined that the cell has been programmed, but has been disturbed. This information results because conduction occurred at the elevated control gate voltage, but did not occur at the lowered control gate voltage, indicating that some of the electric charge has left the floating gate. Thus, step S52 is encountered and the particular memory cell is refreshed.
Because of progress of semiconductor technologies which has been achieved in recent years, the film thickness of an oxide film to be formed under the floating gate electrode 506 of the non-volatile semiconductor memory is about 100 .ANG., and is expected to continue to be further thinned. However, as the oxide film becomes thinner, leak current tends to increase.
In the flash memory as described above, data is stored according to whether an electric charge is present on the floating gate electrode 506 or not. Thus, as semiconductor-manufacturing process becomes finer and the tunnel oxide film becomes thinner, there occurs a problem that the leak current causes the electric charge to easily leave the floating gate electrode 506, resulting in unexpected data erasure. In particular, in a memory for storing quaternary, or 4-valured data (two bits) or octal data, or 8-valued data (three bits), difference between states (difference between threshold voltages Vth of memory cell) is small. Thus, increase of the leak current is a serious problem.
Furthermore, as the manufacturing process becomes finer and the tunnel oxide film becomes thinner, the leak current causes the electric charge to leave the floating gate 506 easily, resulting in poor yield.
Japanese Patent Laid-Open Publication No. 60-74578 discloses a non-volatile memory wherein by incorporating in a memory cells' peripheral circuit a means of storing the number of rewrites of a memory cell, refresh is automatically performed each time the number of rewrites of the memory cell exceeds a predetermined value. In this technique, a user cannot select a refresh timing. Thus, even though the user wants to read or write data, the system is placed in a refresh mode when the number of data-rewriting times exceeds the predetermined value. Thus, the user has inconvenience in using it.
Japanese Patent Laid-open Publication No. 1-134793 discloses a non-volatile memory in which a refresh is performed in response to application of supply voltage.
Also, as described above in detail, the U.S. Pat. No. 5,365,486 (corresponding to Japanese Patent Laid-open Publication No. 7-37397) discloses a non-volatile semiconductor memory in which a potential of a word line is elevated and lowered such that refresh of a particular memory cell is performed based on results of decisions made at two different read voltages.
In any of the known non-volatile memories, the user cannot select a refresh operation or a read operation according to the user's intention. Also, the user is not informed as to whether refresh is being performed. Thus, those non-volatile memories are inconvenient for the user.